Adeas - your developing partner
Adeas - FPGA Design  
Adeas specializes in FPGA design services. Our knowledge and experience with the ins and outs of the latest components, tools and possibilities allow us to implement the most complex algorithms and high speed interfaces. This can be done completely real time in hardware or in combination with a processor core for which optimal code is designed.

Standard policy is to test each FPGA design by means of a specially developed test applications commonly called a test bench.

To save time and money we integrate internal or external Intellectual Property (IP) in our designs. This however is always discussed with our client.

FPGA floorplan
FPGA floorplan

Through the extensive experience of our specialists with the component families of the market leaders and the (im-) possibilities of the design tooling we are able to choose the direction toward an optimal solution in an early stage. This is the case in sub problems like clock domain issues, signal filtering, resource reduction and timing requirements.

We are also familiar with the pitfalls and are able to avoid these. Furthermore we have early knowledge of new features, roadmaps and validated IP-cores and use this knowledge to our and our clients’ advantage.

Technology | Competences
 



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News

September 7, 2017

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Adeas at Design Automation
& Embedded Systems event
2017, October 12th

Adeas exhibits and lectures
at the event on October 12th
2017 in the ‘1931’ congress
centre ’s-Hertogenbosch.
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September 8, 2015
Adeas at Bits & Chips Smart Systems 2015
Adeas exhibits and lectures the event on October 1st 2015 in the '1931' Congress Centre 's-Hertogenbosch.
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June 11, 2015whitepaper_timing_synchronization_through_SMPTE_ST2059.jpg

Download our whitepaper on “Timing Synchronization through SMPTE ST2059”.
Download
 

April 10th, 2015
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Adeas demos Video over IP network synchronization at the NAB show in Las Vegas April 13-16, 2015.

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